日志中没有看到任何异常告警啊:
read_file -format verilog {/home/vectorli/project/dc/lock/lock.v}
Loading db file '/home/vectorli/project/dc/lock/tt_1v8_25c.db'
Loading db file '/eda/synopsys/dc/syn1806sp1/libraries/syn/gtech.db'
Loading db file '/eda/synopsys/dc/syn1806sp1/libraries/syn/standard.sldb'
Loading link library 'tt_1v8_25c'
Loading link library 'gtech'
Loading verilog file '/home/vectorli/project/dc/lock/lock.v'
Detecting input file type automatically (-rtl or -netlist).
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/vectorli/project/dc/lock/lock.v
Inferred memory devices in process
in routine Lock line 30 in file
'/home/vectorli/project/dc/lock/lock.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| clk1_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
| timer1_reg | Flip-flop | 8 | Y | N | N | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine Lock line 37 in file
'/home/vectorli/project/dc/lock/lock.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| charge_on_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
| timer_reg | Flip-flop | 16 | Y | N | N | N | N | N | N |
| unlock_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine Lock line 67 in file
'/home/vectorli/project/dc/lock/lock.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| finish_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
| unlock_1_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
| unlock_2_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully.
Current design is now '/home/vectorli/project/dc/lock/Lock.dbock'
Loaded 1 design.
Current design is 'Lock'.
dc_shell> Current design is 'Lock'.
compile -exact_map
Information: Evaluating DesignWare library utilization. (UISN-27)
============================================================================
| DesignWare Building Block Library | Version | Available |
============================================================================
| Basic DW Building Blocks | O-2018.06-DWBB_201806.1 | * |
| Licensed DW Building Blocks | | |
============================================================================
Information: There are 5 potential problems in your design. Please run 'check_design' for more information. (LINT-99)