|
不知道大侠们能不能给指指路,不知道是怎么会是出现了这些error。
# Loading work.testbench
# Loading work.top5
# ** Warning: (vsim-3009) [TSCALE] - Module 'top5' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT
# Loading work.HSYNC_BLOCK
# ** Warning: (vsim-3009) [TSCALE] - Module 'HSYNC_BLOCK' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/HSYNC_BLOCK
# Loading work.D_FF
# ** Warning: (vsim-3009) [TSCALE] - Module 'D_FF' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/D_FF_HSYNC
# Loading work.VSYNC_BLOCK
# ** Warning: (vsim-3009) [TSCALE] - Module 'VSYNC_BLOCK' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/VSYNC_BLOCK
# Loading work.DATA_OUT
# ** Warning: (vsim-3009) [TSCALE] - Module 'DATA_OUT' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/DATA_OUT
# Loading work.IMAGE
# ** Warning: (vsim-3009) [TSCALE] - Module 'IMAGE' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/IMAGE
run -all
# Success! Annotation Simulation Complete.
# Break at test_top5.ant line 84
run -all
# Break key hit
# Break at test_top5.ant line 37
run -all
# Break key hit
# Simulation stop requested |
|